1. Field of the Invention
The present invention relates to semiconductor devices. More particularly, this invention relates to a semiconductor device having a redundancy circuit and a fuse circuit, as well as to methods of fabricating the same.
2. Description of the Related Art
As design rules of semiconductor memory devices decrease, high-density memory devices (e.g., 256 MB Dynamic Random Access Memories (DRAMs)) have become popular. In high-density memory devices, a memory device will not operate properly even if only one of its many memory cells is defective. Unfortunately, however, as the integration density of DRAMs increases, the probability of a defect occurring in the memory cells also increases. This can therefore significantly decrease the total yield of semiconductor device fabrication, even if only a few memory cells turn out to be defective. In a conventional method of increasing the yield, defective cells are replaced using a redundant memory cell circuit included in each of the semiconductor devices.
This method has been applied primarily to DRAMS (e.g., 64-256 MB DRAMs). According to this method, if main cells are defective, addresses allotted to the defective main cells are replaced by addresses (e.g., column/row lines) corresponding to redundant cells in a redundant memory cell circuit. Accordingly, when a wafer fabrication process is completed, an electrical test is used to distinguish between defective memory cells and normal main cells. The addresses of the defective memory cells are then replaced with addresses of replacement cells in the redundant memory cell circuit through a repair process, such as a laser repair process, for example. The laser repair process is performed by cutting fuses in a fuse circuit that connects main cells to redundant cells.
Accordingly, during operation, when an address corresponding to a defective cell is input, the address of the defective cell is replaced with a preliminary address in the redundant memory cell circuit. The semiconductor memory device can thereby operate properly despite the presence of defective memory cells.
FIG. 1 is a schematic diagram of a conventional semiconductor device having a fuse circuit. Referring to FIG. 1, a general memory circuit (e.g., DRAM) of the conventional semiconductor device, is divided into a cell region 30 and a peripheral region 40. Memory cells are formed in the cell region 30. The number of memory cells corresponds to the storage capacity of the memory circuit. A decoder is used to operate unit cells in the cell region 30. A buffer circuit, a redundancy circuit, and a fuse circuit 14′ are formed in the peripheral region 40. The peripheral region 40 includes all of the regions of the memory circuit except for the cell region 30.
A pad redistribution pattern 22 is a conductive pattern used to redistribute a pad 16 formed under a passivation layer 18 of a semiconductor device. The pad redistribution pattern 22 is used in manufacturing a wafer level package (WLP). FIG. 2 is a cross-sectional view of a conventional semiconductor device used to form a WLP having a fuse circuit. Referring to FIG. 2, a DRAM device having a conventional fuse circuit is manufactured by forming a lower structure 12 on a semiconductor substrate 11. The lower structure 12 can be a DRAM circuit having a cell region and a peripheral region. The lower structure 12 includes a gate electrode, a bit line, a capacitor, and a metal wiring layer (not shown). A pad 16 is formed to provide an external contact for the DRAM circuit. A passivation layer 18 and a first insulating layer 20 are sequentially formed on the resulting structure and are patterned to expose the pad 16.
A pad redistribution pattern 22 is formed on the first insulating layer 20 and is connected to the pad 16. A second insulating layer 24 is then formed to expose a predetermined portion of the pad redistribution pattern 22, to which an external connection terminal can be attached. The external connection terminal used in the WLP process can, for example, be a conductive bump, e.g., a solder ball, or any other suitable external connection terminals.
Unfortunately, conventional semiconductor devices with fuse circuits have several problems. Among others, since a fuse circuit 14 occupies a predetermined area in a peripheral region of a semiconductor memory device, there is a limit to the amount by which the integration density of the semiconductor memory device can be increased. In addition, when manufacturing a small outline package (SOP) or a quad flat package (QFP), there is no need to form the first insulating layer 20, the pad redistribution pattern 22, and the second insulating layer 24 on the passivation layer 18. Accordingly, for these devices, it is not difficult to cut a fuse pattern 14 under the passivation layer 18 using laser beams. When manufacturing a WLP, however, the first insulating layer 20, pad redistribution pattern 22, and the second insulating layer 24 are formed on the passivation layer 18. There is accordingly a much greater distance between the top surface of the semiconductor memory device, to which laser beams are applied, and the fuse pattern 14. Problems may therefore occur during a laser repair process. For example, the laser beams applied to the top surface of the semiconductor memory device may be out of focus. To correct this problem, the width of the fuse pattern 14 is increased. This decreases the integration density of the semiconductor memory device.